1. Field of the Invention
The present invention relates to methods of fabricating semiconductor devices. In particular, the present invention relates to the steps associated with the fabrication of bipolar, Metal Oxide Semiconductor (MOS), and Bipolar Complementary MOS (BiCMOS) structures. More particularly, the present invention relates to those aspects of the fabrication of BiCMOS structures involving the formation of Schottky diodes of selectable characteristics without modification of the existing fabrication steps. The present invention is a "no cost" method of fabricating improved Schottky diode structures.
2. Description of the Prior Art
In an effort to create increasingly faster semiconductor devices that consume less power, it is a goal in the semiconductor industry to create increasingly smaller integrated circuit (IC) devices. This relates to the interest in creating IC devices requiring lower supply voltages; that is as device power supplies move from a nominal 5.0 volts to a nominal 3.3 volts, to a nominal 2.0 volts and less. To that end, the steps associated with the fabrication of IC devices are becoming more critical and complex. With increasing complexity and criticality comes significant potential for a decrease in productivity, including greater fabrication costs and lower device yield. It is therefore a continuing goal in this field to minimize fabrication steps and the time and errors associated therewith.
Improvements are sought in all areas of semiconductor fabrication, particularly so in advanced processes. In the field of advanced BiCMOS devices for example, the integration of the steps associated with the formation of bipolar devices and MOS devices creates the type of complexity that requires considerable fabrication coordination. The addition of more masks, implants, depositions, etchings, and the like for advanced BiCMOS processing increases the costs associated with raw materials, capital equipment, and direct and indirect labor obligations.
As power source potentials decrease, there will be a rise in the need for P-N junction devices such as P-N diodes having lower forward turn-on potentials (Vf) with relatively low reverse bias leakage currents (Ir). In that regard, most existing P-N junction devices have Vf and Ir values that would otherwise be unacceptable in systems powered by voltage sources having a nominal potential of 3.3 volts or less, for example. Specifically, most such junction structures have a Vf of about 0.75 volts for a forward current (If) of about 1.0 .mu.A/.mu.m.sup.2. That turn-on potential offers little leeway as the swing between high and low logic levels decreases with lower potentials of the high-potential power rail. It is also to be noted that reverse leakage current leads to power consumption out of line with the importance of most P-N junction diodes as power availability is reduced.
Schottky diodes, formed at the junction of metal-silicon interfaces, can provide a solution to the turn-on voltage limitations of standard P-N diodes. In BiCMOS fabrication processes they are formed at the surface of an active region of the semiconductor wafer by depositing a metal such as Titanium or Platinum onto an area doped with a dopant at a selected concentration. The metal and the silicon react at the surface of the active region under thermal annealing conditions so as to form a metal-silicide layer. For the most part, Schottky diodes are made with an underlying layer of N-type dopant forming the cathode. Of course, a P-type dopant may also be employed to establish the cathode region of the Schottky diode. In either case, it is generally preferable to provide the cathode region with dopant at a concentration somewhat less than that of source and drain regions of a CMOS structure, for example, in order to provide suitable resistance and capacitance characteristics.
It has been determined that of the two metals noted above, the application of Titanium to create a Titanium-silicide (TiSi2) anode may be used to produce a Schottky diode having a Vf equal to about 0.28 volts at If=1.0 .mu.A/.mu.m.sup.2. However, its Ir is about 80 .mu.A/.mu.m.sup.2 --a value considered to be too high for the lower-potential supply rails coming on line. Alternatively, a Platinum-silicide (PtSi) anode has an Ir of only about 0.004 .mu.A/.mu.m.sup.2, while its Vf is unacceptably high at about 0.60 volts at If=1.0 .mu.A/.mu.m.sup.2. Therefore, it would be desirable either to adjust the TiSi2-based Schottky to have a lower Ir with substantially the same Vf, or to adjust the PtSi-based Schottky to have a lower Vf with substantially the same Ir.
Several techniques have been described as means to improve some characteristics of Schottky diodes including silicided anodes. These techniques are described, to an extent, in U.S. Pat. No. 4,310,362 issued to Roche et al. and U.S. Pat. No. 5,150,177 issued to Robinson et al. Roche apparently shows that a surface implant may be used to modulate electrical performance. Robinson teaches modulation of the Vf of a Schottky diode using the epitaxial layer as a substrate and with additional doping thereof. However, neither teaches the need to provide the capability to resolve both the Vf and the Ir deficiencies of increasing importance with the continuing trend toward lower-potential supply rails. As importantly, they are riot "no cost" solutions for fabricating suitable Schottky diode structures. Robinson in particular requires additional process steps and modifications to generate a Schottky with lower turn-on values. Therefore, in general, while other solutions may be contemplated to resolve these deficiencies, it is important and preferable that they be resolved substantially within the context of existing fabrication steps so as to avoid adding cost to the process of making a suitable structure.
It is well known that in order to establish desired conductive and non-conductive regions that re designed to either be coupled to, or isolated from, one another, many fabrication steps are required. Although there are any number of fabrication processes suitable for the formation of completed semiconductor devices including Schottky diodes, a summary of 20 major processing events in an exemplar BiCMOS process are set out below, with a brief description of the steps to follow. Those steps, identified by the mask designations noted, are substantially as follows:
Mask No. Mask Function 1.0 N+ Buried Layer Mask 2.0 P+ Buried Layer Mask 3.0 Composite Mask 4.0 Sink Implant Mask 5.0 Channel Stop and PWell Mask 6.0 P-type Anti-punch Through & Threshold Adjust Mask 7.0 N-type Anti-punch Through & Threshold Adjust Mask 8.0 Base Definition Mask 9.0 N+ Polysilicon Exclusion Mask 10.0 Polycrystalline Silicon Gate Definition Mask 11.0 N LDD Mask 12.0 P LDD Mask 13.0 P+ Source/Drain Definition Mask (PMOS) 14.0 N+ Source/Drain Definition Mask (NMOS) 15.0 Salicide Oxide Mask 16.0 Contact Definition Mask 17.0 METAL 1 (M1) Definition Mask 18.0 VIA Definition Mask 19.0 METAL 2 (M2) Definition Mask 20.0 Bond Pad Definition Mask
Of course, each one of the noted steps includes a plurality of sub-steps, some more so than others. While there are many steps and stages associated with the complete fabrication of an integrated circuit on a semiconductor wafer, a number of the mask stages set out above and described briefly herein are directly applicable to the present invention.
Initially, alignment keys are established in the wafer to align all subsequent steps. Next, for a BiCMOS device including an NPN bipolar transistor, for example, a buried collector layer is created on the substrate of semiconductor material noted above. For that particular type of bipolar transistor, a substrate of P type semiconductor material is used. This is accomplished by introducing, such as by implantation, an N concentration of relatively slow diffusing N type atoms to form an underlying layer for subsequent retrograde diffusion in the substrate. At the same time, a second buried N type layer is formed as an NWell in the substrate to underlie the region to become the PMOS transistor of the BiCMOS device. Similarly, a buried layer of P type dopant is formed in the region of the substrate to underlie what will become the NMOS transistor of the BiCMOS device. This P type buried layer is formed in between the two N type buried layers and electrically isolates them from one another. Additionally, the P type atoms are introduced into areas adjacent to the buried N type layers previously introduced so as to form channel stops for isolation of adjacent active areas.
Next, an epitaxial layer in the form of single crystal N type semiconductor material in an N.sup.- concentration is formed over the buried layers. This is achieved by introducing a silicon-containing fluid, usually silane gas, in a thermal process that causes silicon growth on the surface of the original substrate. However, rather than provide an epitaxial layer of the same conductivity as that of the substrate, conductive elements are introduced with the silicon-containing fluid during that thermal stage. The conductive elements are generally elemental dopants including, but not limited to, phosphorous, boron, arsenic, and antimony. The amount of dopant material introduced with the silane may be different from one particular process to another; however, it is generally introduced in a chemical vapor deposition process including a steady-state flow condition that establishes what is initially designed to be a uniform epitaxial layer conductivity.
The epitaxial layer is grown to a desired thickness and it forms the foundation for the remaining steps used to fabricate the various regions of the device. Integrated circuit fabrication techniques involving the formation of the epitaxial layer usually introduce enough conductive elements such that the dopant levels in the epitaxial layer are on the order of about 1-3.times.10.sup.15 atoms/cc to about 1-3.times.10.sup.16 atoms/cc.
Other integrated steps are used to form the bipolar transistor. In particular, a collector sink of relatively fast-diffusing N type atoms is introduced into the epitaxial layer above a portion of the buried N layer used for subsequent collector development. The collector sink is created by depositing the N type atoms on the epitaxial surface, or more commonly, by implanting those atoms into the surface. Subsequent annealing drives the atoms down into the epitaxial layer to establish in some fashion a desired dopant profile in that region in conjunction with the buried layer. The combination of the buried layer and the sink establish the bipolar transistor's collector. Of course, the same could be done for a PNP bipolar transistor using P type materials to form that buried layer and the collector sink.
In the generic BiCMOS process presented, formation of the MOS transistor structures requires the fabrication of conductive wells, and the gate, source, and drain components of the NMOS and PMOS transistor structures. Additionally, formation of the bipolar transistor structures requires the fabrication of the base, emitter and collector components. For the MOS structures, the PWell is formed on the buried layer of P type material and allowed to diffuse toward the surface of the epitaxial layer during the PWell and Channel Stop Mask implant and thermal processing steps. It is to be noted that the epitaxial layer in the region of the PMOS transistor acts as an NWell for that structure.
Isolation oxide layers are next formed about the MOS transistor structures by conventional mask, etch, and formation sequences so as to isolate them from adjacent structures. The field oxide regions are formed are formed above the isolation regions using a field oxide region definition mask in order to further isolate adjacent structures. Channel stop regions, formed at the same time and of the same atom type as the PWell, underlie the isolation oxide regions surrounding both the NWell and PWell. The channel stops isolate the wells from parasitic MOS effects caused by adjacent structures.
Continuing with the summary description of this exemplar BiCMOS process, formation of the MOS transistor structures requires the fabrication of the gate, source, and drain components of the NMOS and PMOS transistor structures. Additionally, formation of the bipolar transistor structures requires the fabrication of the base, emitter and collector components. For the MOS structures, the gates are formed of a polycrystalline layer of semiconductor material, using a well-known mask, etch, and deposition sequence. This "polysilicon layer" is formed on the surface of the respective wells, but is separated from the well surfaces by an underlying gate oxide layer. In the BiCMOS process, the polysilicon layer is used to form polycrystalline silicon gates of the MOS transistors and a polysilicon emitter of the bipolar transistor upon suitable subsequent implanting. The gate oxide layer acts as a dielectric, insulating the gate of the particular MOS transistor structure from the source, the drain, and the channel lying therebetween. The integrity of this gate oxide layer must be maintained throughout the integrated fabrication process so as to ensure effective transistor operation.
In order to accommodate the different characteristics of the two types of transistors without degrading the quality of either, it has been determined that there are advantages in creating the polysilicon layer in two separate steps. This "split poly" process involves the introduction of a relatively thin layer of polycrystalline silicon over the gate oxide layer in a blanket deposition. Subsequent processing steps are used to dope underneath the first polycrystalline silicon layer in the channel region for PMOS and NMOS threshold voltage development and for anti-punch through protection. On the bipolar side, relatively slow diffusing P type atoms in a P+ concentration are implanted into the surface of the epitaxial layer through the first polycrystalline silicon layer while the collector sink and CMOS active areas are protected by photoresist.
After poly gate formation, a sealing oxide is formed on the surface of the gates and on the active regions of the MOS wells. This thermally grown sealing oxide protects the gates and CMOS wells during subsequent implantation steps used to form the "lightly-doped drain" (LDD) regions previously mentioned. Specifically, a relatively fast-diffusing N type atom in an N concentration (N LDD) is shallowly implanted in the surface of the PWell and a relatively fast-diffusing P type atom in a P concentration (P LDD) is shallowly implanted in the surface of the NWell. These initial implants are designed to extend slightly beyond the final dimensions of the source and drain regions, resulting in an effective gate channel length in the range 0.4-0.6 micron. In addition to initiating the formation of the well-defined source and drain regions, the shallow LDD also provides a gradual transition from source or drain to the channel region, thereby reducing hot electron effects. Of course, with the much smaller structures fabricated today, the importance of the LDD in reducing hot electron effects increases. The LDD regions are less heavily doped than the specific source and drain regions, but more heavily doped than the insulative oxide regions immediately adjacent to the active areas. It is this portion of the fabrication process that is related to the creation of the Schottky diode structure of the present invention.
In order to produce shallower, and therefore faster, devices, and properly sized source and drain regions, a spacer oxide is deposited to a thickness of about 2000 .ANG. over the future source and drain regions and the poly gates. The spacer oxide is then etched to expose substantially all of the active areas of the device during the silicide exclusion step. Etching of the spacer oxide exposes the top of the gate and the subsequent source and drain regions for following ion implants and metal deposition. Relatively slow-diffusing P type atoms in a P.sup.+ concentration in the surface of the NWell and relatively slow-diffusing N type atoms in an N.sup.+ concentration are then introduced into the surface of the PWell, using conventional mask, etch and implant sequences, to define the source and drain regions of the PMOS and NMOS transistor structures respectively.
After implantation of the source and drain regions, a preliminary conduction layer is defined by the metal-silicon combination previously described in regard to the formation of the silicide layer that provides a smooth transition between silicon-based layers of the active area and metal contacts. This aspect of the exemplar BiCMOS fabrication process also relates to the present invention. In any event, in the general processing scheme, conventional bond pads that are the metal contacts are formed in order to couple the transistors to external circuitry, including by way of input/output nodes.
For the bipolar side of the process, as noted, the emitter region is subsequently formed over the base region during the blanket polysilicon gate sequences. During the formation of the source and drain regions of the PMOS structure, an extrinsic base region is established over the intrinsic base region surrounding the poly emitter located on the surface of the epitaxial layer. Remaining steps include final formation of isolation and metal contact regions.
For high performance BiCMOS processes similar to that described briefly herein, silicide is typically used for various electrical advantages. That silicide may also be used to form a Schottky diode. However, in order to keep parasitic capacitance low (for PMOS and bipolar devices), the NWell is generally preferably doped at relatively low doping concentrations which may not otherwise provide optimal cathode doping if used as a Schottky diode substrate in association with the silicide. This is particularly so as power supply voltages are scaled down. Therefore, what is needed is an improved Schottky diode structure having a relatively low turn-on threshold and a relatively low leakage-current characteristic. What is also needed is an improved fabrication sequence that enables the formation of such an improved Schottky diode structure. Further, what is needed is such an improved fabrication sequence that involves little modification to existing sequences and thereby adds effectively no cost to the process of forming such an improved structure.